01 / EMBEDDED
Digital logic in VHDL, Verilog and SystemVerilog for acquisition, processing and interfaces, with testbenches and hardware/software integration.
Platforms and tools follow your context. Some examples:
Embedded
Digital logic, simulation and integration
VHDL · Verilog · SystemVerilogSynchronous logic and modules
States · pipelines · datapathsLogic organisation
Stimuli · checks · scenariosBehaviour verification
Constraints · domains · latenciesPath analysis
Buses · signals · peripheralsSystem data exchange
Control · firmware · diagnosticsVerification on the platform
The technologies shown are examples.
Engineering support within your team, with shared tools and working methods.
TECHNICAL SCOPE
Design starts from frequencies, throughput, latency and available signals. The split between programmable logic and firmware considers parallelism, resources and testability. Simulation and implementation are compared so correct testbench behaviour does not conceal timing or reset problems.
I clarify electrical and logical interfaces, clocks, resets, numerical precision and the existing synthesis flow. Work can cover an HDL block, verification or software integration, following the team’s conventions and review process.
For an acquisition path, expected and produced data, resets and boundary conditions are compared. Functional simulation, clock-domain crossing analysis and static timing serve different purposes. A testbench does not replace CDC analysis or implementation timing constraints.
HDL sources, testbenches, constraints, synthesis instructions and verification results. Acceptance frequency, latency and throughput refer to the agreed FPGA and configuration.
Provide the FPGA device, toolchain, signal specification and sample data to process.
Yes, when hardware, access and documentation allow a focused engagement. Scope can cover only HDL, a testbench or the firmware interface.
SLX EchoBench connects synthetic ultrasound, ThreadX firmware and RTL verification through Renode, Verilator, Godot and C++20. Explore the 3D bench, reproduce FIFO overflow and compare firmware on the same saved input. Windows preview on GitHub.
Where low-cost FPGAs fit in embedded prototyping, digital logic validation, custom IO, soft cores and open-source development flows.
THE NEXT STEP
